Innovative Approaches to Low-Cost Multiplier Design Using Approximate Computing and Clock Gating

In this paper, we propose a novel design methodology for low-cost approximate radix-4 booth multipliers that significantly reduce energy consumption in error-tolerant signal processing applications. Unlike prior works that focus solely on either partial product generation (PPG) or partial product accumulation (PPA), our approach co-designs these units to balance approximation errors, resulting in an internal error mean that is nearly zero. This integration enables substantial energy savings while maintaining comparable accuracy to existing designs. To further enhance energy efficiency, we incorporate a Synthesized-based clock gating technique, reducing unnecessary switching activity in the design. Experimental evaluations on Finite Impulse Response (FIR) filtering and image classification tasks demonstrate that the proposed multiplier achieves up to 39.3% reduction in total power consumption while maintaining accuracy within an acceptable range for error-tolerant applications. Additionally, delay and area utilisation are reduced by approximately 15.18% and 8.26%, respectively, compared to the existing method. Compared to traditional accurate booth multipliers, our design provides a better trade-off between power efficiency and computational precision, making it a promising alternative for energy-constrained digital signal processing (DSP) systems.