FPGA Implementation of Floating-Point Multiplier Employing Carry-Lookahead Adders

For hardware implementation of digital signal processing algorithms, the key components are multipliers. The design of multipliers plays an important role in overall system architecture. For algorithms requiring a dynamic range of data, floating-point representation is favoured over fixed-point. Nevertheless, floating-point multipliers provide difficulties for designers because of the large latency and space that they need. In this work, we suggest a more efficient method of floatingpoint multiplication with respect to both time and space. The bottleneck in the floating-point multiplier design is the Mantissa multiplication which is implemented through fast tree multipliers. Instead of using half-adders and full-adders as in conventional Wallace or Dadda tree multipliers, Carry-lookahead adders are used as compressors in the proposed structure, which resulted in a better partial product reduction in mantissa multiplication. The proposed design is validated through FPGA implementation using Verilog HDL description. It was observed that an improvement of 8.5% with respect to Wallace and an improvement of 9.9% with respect to Dadda is obtained in terms of latency.