Ternary Adder and Multiplier Circuit Designs with GNRFET and RRAM Technologies

To address the limitations of binary logic and keep pace with the demand for higher density, processing capabilities, and energy efficiency, researchers have explored various technologies. Ternary logic technique, which utilizes three logic states (0, 1, and 2), has emerged as a promising candidate. In this work, ternary logic half adder and multiplier circuits are implemented using a combination of graphene nanoribbon field-effect transistors (GNRFETs) and resistive random-access memory (RRAM). The GNRFETs offer excellent electrical properties, while RRAM provides a robust option for storing multiple resistance states in a single cell. The proposed half adder and multiplier circuits are designed using basic gates, universal gates and decoder circuits, respectively. The circuits are simulated using the HSPICE simulator with a supply voltage of 0.9 V. The performance of the proposed GNRFET and RRAM based ternary logic circuits is compared with existing carbon nanotube FET (CNTFET) and RRAM based ternary circuits. The proposed circuits exhibit significant improvements in terms of power, delay, and power-delay product (PDP) up to 50.09%, 28.29% and 64.53%, respectively than the CNTFET and RRAM based circuits.