Improved Positive Feedback Source Coupled Logic Based Tri-State Buffer and Its Applications

An improved PFSCL tri-state buffer design for low-voltage and low-power applications using Dynamic Threshold Voltage MOSFETs (DTMOS) is presented in this work. By using DTMOS transistors for traditional pull-down transistors, the suggested design lowers the threshold voltage and total supply voltage needs. Due to this development, the circuit can function at a lower supply voltage of 1.4 V. With applications shown in bus realization and D-Latch configurations, a comparison analysis between the proposed PFSCL tri-state buffer and available designs is carried out to evaluate the efficacy of the proposed design. Through comprehensive SPICE simulations using 45nm GPDK CMOS technology parameters, the functionality of both designs is confirmed.