Design and Implementation of Efficient 32-Bit Vedic Multiplier

This proposed work specifies a version of the Vedic multiplier designed for large numbers using principles from the ancient technique of Vedic multiplication. A Vedic multiplier is a preferred choice as it demonstrates improvements in speed, area, hardware complexity, power consumption, and scalability. Implementation is performed using Verilog HDL on the Modelsim tool, while Xilinx is utilized for circuit architecture. This study examines three 32-bit Vedic multiplier designs-the Carry Save Adder, the Carry Lookahead Adder, and the Ripple Carry Adder-using various adder architectures. All three designs consumed similar power, approximately 0.082W. The 32-bit CLA-based Vedic multiplier is the fastest, with a delay of 26.466ns, and all had nearly identical power consumption. In terms of area utilization, the RCA-based multiplier was the most efficient Vedic multiplier. Index Terms—High-speed multiplication, Power consumption, Vedic mathematics, Parallel processing, Circuit design.