A Minimalist MOS-Based Meminductor Emulator Circuit

A simple grounded meminductor emulator (MIE) based on a MOSFET configuration is presented in this paper. With six MOSFETs and two capacitors, the proposed circuit may efficiently create pinched hysteresis loops (PHL) at frequencies up to 100 KHz. The dependability of the design is confirmed by thorough analyses that include PVT assessments, which refer to modeling chips at various process, voltage, and temperature corners and non-volatility testing. Simulations were performed with 180 nm CMOS technology characteristics in CST (Cadence Spectre Tool). The consumption of power is a few microwatts in the proposed MIE. A comparative analysis of existing designs illustrates the benefits of the proposed MIE circuit.