An Efficient Radix-8 Factored Systolic Array for Machine Learning Acceleration

This research shows that there is a lot of room for improvement at the logic level, even if SAs have a common structure, and it suggests two new SA that use factoring and radix-8 multipliers. Eliminating shared hard-multiple generation and booth encoding across all Processing Elements (PEs) may assist to reduce the overall size and time of the SA. The proposed method employs a parallel prefix adder to finish the addition of a radix-8 multiplier at each processing element. We refer to this design as Factored Systolic Arrays (FSA). Furthermore, we use Kogge-stone (KS), a parallel prefix two-operand adder that significantly decreases critical route time while requiring extra hardware.It has low gate complexity and high performance. In comparison to the usual radix-4 SA, the suggested FSA design reduces space, power consumption, and latency over a wide range of bit widths. Modelsim is used to conduct simulations of the suggested design, which was produced in Verilog HDL. Xilinx ISE is used to provide a comparative study of current and future techniques.