n-Bit ALU using CMOS Forced Transistor Stacking

This paper proposes the design of an n-bit ALU using CMOS Forced Transistor Stacking, emphasising its performance based on power consumption and delay compared to CMOS circuits. While CMOS designs are widely used, they suffer from high power consumption and latency. In comparison, Forced Transistor Stacking boosts the effective resistance under idle conditions and reduced leakage power by connecting transistors in series. Each block of the suggested ALU design is made up of forced stack transistor circuits and is intended to carry out fundamental arithmetic and logical operations. Using Cadence Virtuoso for simulation and evaluation, this paper highlights the advantages of stacked transistors based on parameters like delay, power consumed and transistor count. The potential of forced transistor stacking as a practical technique for upcoming low-power VLSI designs is highlighted in the study. It exhibits advantages in reduced power leakage, increased power efficiency, scalability for dense systems and thermal benefits. These features make this technique an attractive solution for modern, low-performance, and high-performance digital systems.