Capacitive noise coupling modelling from power plane to signal trace at VRM region and its mitigation

In this paper, capacitive noise coupling is demonstrated with a possible solution. Due to the ripple voltage at the voltage regulator module(VRM) section, significant noise is observed at the VRM input side as the ripple voltage of peak-to-peak 700mV. Signal traces are routed over the VCCGT-Vin plane at L4, where noise input voltage gets coupled to the trace. This leads to a power reset of the platform, during 3D benchmarking.To reduce the coupled noise, various mitigation plan is investigated using signal-power plane co-simulation using Ansys dynamic linking. By using a series inductor at the input of VRM, the significant amount of noise is reduced on signal traces.