Challenges & Solutions with System analysis for UCIeA Power delivery & Power Integrity in 3DIC AI Chip

Universal Chiplet Interconnect express (UCIe) is an open, multi-protocol capable, on-package interconnect standard for connecting multiple dies on the same package. UCIe allows flexibility of mixed-foundry integration with different dies in multiple foundry nodes. Silicon bridge is a promising advanced package that can achieve high bandwidth with high channel density. EMIB being a silicon bridge is key solution for low parasitic high-density interconnect between chiplet. Power delivery & power Integrity is the highest challenge in meeting UCIe electrical requirements as the EMIB bridge shadows the Phy region restricting the direct power delivery connection to Phy from the package. This paper discusses UcieA Phy Power Delivery (PD) & Power Integrity (PI) challenges meeting PD/PI specification and solutions to meet the IP performance and specification. The paper also brings out challenges and mitigation when this IP is developed in 3DIC multi chiplet SOC design as power is delivered from Through Silicon Via (TSV). Also, this paper discusses the modelling & simulation methodology used for this standard protocol.