Parametric study of factors effecting PMIC-QFN reliability under temperature cycling in DIMM systems

In Dual Inline Memory Module (DIMM), Power Management Integrated Circuit (PMIC) is one of the key components used to manage the power of the module. From DIMM validation results it is observed that Solder Joint Reliability is the key concern for PMIC-QFN(Quad Flat No lead) packages under temperature cycling. One of the common failure modes in PMIC QFN packages is solder joint crack due to CTE mismatch between the Package elements and PCBA under temperature cycling. To mitigate this issue and reduce the strain energy developed in PMIC QFN, it is crucial to study the effect of key parameters of PMIC QFN interconnect and placement of PMIC component on PCBA. In this paper detailed study of effect of critical parameters such as QFN solder geometry parameters, PCB material, PMIC mold compound, effect of various components underneath PMIC, effect of underfill and various combinations of packages with underfill and corner fill are presented. A parametric APDL script (Ansys Parametric Design Language) is written to automate the generation of finite element models required for the study. The study gives the guidelines for placement of PMIC Package on DIMM systems and ways to improve the reliability of the QFN solder joints.