Advanced Low-Power Hybrid Full Adder Design using MUX Transmission Gates and Dynamic Sleep Signal in MTCMOS Technology

The increasing demand for low-power electronic devices has necessitated innovative circuit design techniques to minimize power consumption while maintaining high performance. In arithmetic circuits, the full adder is a fundamental component, widely used in applications such as Digital Signal Processing (DSP), Digital Image Processing (DIP), Wireless Sensor Networks (WSN), Satellite Communication, and Arithmetic Logic Units (ALU). Conventional full adder designs suffer from high power dissipation and increased leakage currents, limiting their efficiency in low-power applications. This research addresses these challenges by proposing a 1-bit hybrid full adder that integrates transmission gate logic and XOR logic with Multi-Threshold CMOS (MTCMOS) technology. The key novelty of this design is the incorporation of a dynamic sleep signal for the sleep transistors, which significantly reduces static power consumption to negligible levels. The proposed design was implemented using Cadence Virtuoso with a 90nm GPDK technology node. Performance evaluation demonstrated a dynamic power consumption of 2.03906 μW, a critical path delay of 2.4963 ns, and a power-delay product (PDP) of 5.0918 fJ, indicating superior efficiency compared to existing designs. The results validate the effectiveness of the dynamic sleep-based MTCMOS approach, making it a promising solution for energy-efficient VLSI circuit design.