Modeling of Eye Diagram for Jitter Estimation in Presence of Ground Bounce

The developed method in this paper presents an analytical approach for combined modeling of rising and falling transition edges to estimate jitter using an eye diagram in the presence of ground bounce noise (GBN) in a CMOS inverter circuit. Analytical expressions are derived for all operational regions of the inverter transistors and varying input waveform slopes, establishing a comprehensive input-output relationship. The proposed model is validated through practical case studies for jitter estimation, specifically focusing on rising transition edges, and is further employed to model the eye diagram. The methodology is verified using 40 nm technology nodes from United Microelectronics Corporation (UMC), demonstrating strong correlation with simulation results.