Robust Design Optimization applied to unit warpage analysis of exposed die flip-chip package

With the development of electronic packaging technology, demand for flip-chip interconnect technology is being driven by a number of factors from all corners of the semiconductor industry, and flip-chip technology provides a direct and efficient bond between chips and substrates, replacing traditional wire interconnections. Moreover, the exposed die flip-chip package can be produced due to its thin thickness and thermal dispersion, and the warpage behavior of the exposed die flip-chip package plays an important role in design stage. To control and optimize the warpage of the exposed die flip-chip package, this study is aims to test the ability of the software combination finite element method (FEM)/optimization module to handle a complex stacking/material relation with a significant number of parameters for parametric optimization. The result shows that the main factors affecting warpage are die thickness, thickness of equivalent copper circuit layer, coefficient of thermal expansion (CTE) of copper and coefficient of thermal expansion of compound at reflow temperature. Then the optimization analysis provides a process that is adopted for an evolutionary algorithm in the complete defined parameter range and it starts with 4 input parameters and output warpage results of room/reflow temperatures to find the parameter combination that has the best warpage performance. Finally, a robustness analysis around the best design is performed, and the distribution of warpage and failure probability are found.