Signal Integrity (SI) Analysis and optimization of a 20-slot Aggregation router’s recurring fabric link field failures

This paper investigates the recurring fabric link failures and errors that multiple customers have reported in a 20-slot Aggregation router after migrating to new-generation, higher data rate, line cards. A comprehensive Bit Error Rate (BER) analysis was conducted at 43.75Gbps PAM4 on various customer returned failure analysis (FA) chassis, revealing significant BER discrepancies amongst them. The root cause was identified as a combination of two factors: higher insertion loss in the backplane Printed Circuit Board (PCB) due to an uncontrolled process for insertion loss specifications, and increased crosstalk in the backplane connector caused by the constraints of the connector component used. These findings highlight the necessity for stringent control over insertion loss (IL) specifications during manufacturing and a reconsideration of connector component design to mitigate crosstalk, thereby enhancing system reliability. While the paper presents the observations and solutions in a linear fashion, the debug effort wasn’t so. In the absence of the original designers of the system, most of the effort involved reverse engineering and retrofitting the analysis to the collected evidence to come to the plausible conclusion.

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Publication Details

Published
2024-12-17
DOI
https://doi.org/10.1109/edaps64431.2024.10988482
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

Signal Integrity (SI) Analysis and optimization of a 20-slot Aggregation router’s recurring fabric link field failures

Sameer Joshi, N. Balaji, Bala Sirish Chaturvedula
VLSI and Analog Circuit Testing
article

Signal Integrity (SI) Analysis and optimization of a 20-slot Aggregation router’s recurring fabric link field failures

Sameer Joshi, N. Balaji, Bala Sirish Chaturvedula
article en

Abstract

This paper investigates the recurring fabric link failures and errors that multiple customers have reported in a 20-slot Aggregation router after migrating to new-generation, higher data rate, line cards. A comprehensive Bit Error Rate (BER) analysis was conducted at 43.75Gbps PAM4 on various customer returned failure analysis (FA) chassis, revealing significant BER discrepancies amongst them. The root cause was identified as a combination of two factors: higher insertion loss in the backplane Printed Circuit Board (PCB) due to an uncontrolled process for insertion loss specifications, and increased crosstalk in the backplane connector caused by the constraints of the connector component used. These findings highlight the necessity for stringent control over insertion loss (IL) specifications during manufacturing and a reconsideration of connector component design to mitigate crosstalk, thereby enhancing system reliability. While the paper presents the observations and solutions in a linear fashion, the debug effort wasn’t so. In the absence of the original designers of the system, most of the effort involved reverse engineering and retrofitting the analysis to the collected evidence to come to the plausible conclusion.

Cisco Systems (China) (CN)
Openalex Percentile: Top 67%
VLSI and Analog Circuit Testing
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