Fully-Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R-Based Layout Automation Framework

This paper presents two fully standard-cell-based synthesizable Successive-Approximation- Register Analog-to-Digital Converters (SAR ADCs) and the automated layout generation framework. The 1st design is an 8-bit charge-redistribution SAR ADC. A 4-inverter-cell-based analog switch is proposed, effectively mitigating charge injection/absorption in the capacitive digital-to-analog converter. This prototype is fabricated in a 65 nm CMOS process and occupies 0.095mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. With a Nyquist input, the ADC achieves 55.8 dB spurious-free dynamic range (SFDR) and 47.7 dB signal-to-noise-and-distortion ratio (SNDR) at a sampling frequency of 33.3 MS/s without calibration. The power consumption is 0.91mW, achieving Walden Figure of Merit (FoMW) of 0.13 pJ/conversion-step. The 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> design is a 12-bit 2-stage pipelined SAR ADC, where a standard-cell-based amplifier is proposed to amplify the residue voltage after the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage conversion. This prototype is fabricated also in a 65 nm process and occupies 0.136 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. With a Nyquist input, the pipelined ADC achieves 72.1 dB SFDR and 63.1 dB SNDR at a sampling frequency of 22.2 MS/s with a simple foreground calibration of the inter-stage amplifier gain. The power consumption is 2.7mW, yielding a FoMW of 0.105 pJ/conversion-step. A layout automation framework based on placement and routing (P&R) tool for the standard-cell-based ADCs is proposed and demonstrated with the 8-bit SAR ADC design as an example.