Enhanced Simulation Accuracy and Design Optimization in Power Semiconductors Through Individual Aluminum Metallization Layer Modeling

This study investigates the impact of modeling the aluminum (Al) metallization layer as an integrated part of the chip model, versus as an individual component, on the results of electrical–thermal analysis of power semiconductor packages using Finite Element Analysis (FEA), ANSYS 2024 R2. The results showed that modeling the aluminum metallization layer separately exhibited high consistency with actual thermal imaging data. Furthermore, based on these findings, we observed through simulations that the aluminum metallization layer plays a key role in improving the uniformity of current density and temperature distribution within the chip. Using the aluminum metallization layer model, we optimized the thickness, material, and design of the metallization layer, as well as the bonding wire material through the design of experiments (DOE) methodology. Under the optimized conditions, an optimal design is proposed to minimize the voltage–current ratio (VDS/IDS), maximum junction temperature, strain, and von Mises stress. This study systematically examines the influence of aluminum metallization layer modeling on FEA-based power semiconductor package simulations and is expected to serve as a valuable reference for future power device design utilizing finite element analysis.