Indigenous Design and Implementation of Power-Efficient Multiplier using Field Programmable Gate Array

The main problem with digital design across various applications is the design of power-efficient circuits. Many different methods and techniques were designed in the past to boost speed while lowering power consumption. In this research article, authors designed conventional multipliers like vedic, array, and Wallace tree multipliers (WTM)) using adders with OR-AND- Invert (OAI) and NOR logic for varying bit lengths (4-bit, 8-bit, and 16-bit). Out of various multipliers, WTM shows remarkable results. The power density, digital circuit complexity, and heat dissipation increase in conventional multipliers. To reduce these issues authors proposed a WTM using a half adder, full adder, 4:2 compressors, and 4-bit adder in one circuit. 2.021 W power was observed for the proposed WT multiplier for 4-bit while 3.684W was observed for the WT multiplier using OAI logic and 2.422W considering NOR gate technology. The results were also compared based on the look-up tables, slices, and input-output buffers. All the simulations were carried out in VIVADO software using Verilog HDL and the results were synthesized on the Zynq board of Field Programmable Gate Array. The designed circuits can be used in various Image/signal processing applications.