Advancing semiconductor integration: 3D ICs and Perylene-N as superior liner material for minimizing TSV clamour coupling

The semiconductor industry faces substantial challenges with planar integration (2D ICs), prompting a significant shift towards vertical IC integration, known as three-dimensional IC (3D ICs). This deliberate slant not only amplifies bandwidth and boosts system action but also effectively reduces power consumption through scaling. 3D ICs intricately coordinate IC chips by vertically stacking them and establishing electrical connections using through silicon vias (TSVs). TSV clamour coupling emerges as a critical factor influencing system performance, particularly between signalcarrying TSVs (ETSV) and victim TSVs. This study showcases significant advancements in electrical integrity by effectively minimizing clamour coupling from TSVs to the silicon substrate. This is achieved through the application of CMOS-compatible dielectric materials as liner structures. Various proposed structures have been meticulously analyzed across an assortment of parameters, encompassing electrical signals and high frequencies. Moreover, the study rigorously investigates clamour coupling across different types of TSVs, including ETSV, thermal TSV (TTSV), and heat sources. Perylene-N emerges as a standout performer among the tested liner materials, demonstrating superior clamour coupling performance across all proposed models, even at higher frequencies such as THz. In this study a novel dielectric material Perylene-N compared with the conventional SiO2 (silicon dioxide). Notably, Perylene-N exhibited a remarkable 33 dB improvement in noise coupling performance at terahertz (THz) frequencies. The results were thoroughly verified and validated in the research work.