Non‐Uniform Voltage Balancing Methods for Series‐Connected SiC MOSFETs in High‐Frequency Fast Switching

ABSTRACT A half‐bridge circuit formed by series‐connected silicon carbide metal‐oxide‐semiconductor field‐effect transistors (SiC MOSFETs) generates high‐frequency, high‐voltage pulses with a fast rising time, widely used in electro‐optical modulators. Inconsistencies in the drive circuit timing, variations in device parameters, and parasitic parameters in drive circuit lead to non‐uniform switching behaviour among the SiC MOSFETs, causing significant voltage stress disparities and potential overvoltage breakdown under severe conditions. The limitations of traditional passive balancing methods are addressed, where reduced switching speeds and increased losses are caused by identical balancing circuits. A novel non‐uniform resistor‐capacitor‐diode (NRCD) voltage‐balancing method is proposed for the load side. Considering the influence of parasitic parameters of the drive circuit, the optimal matching of circuit voltage balancing is realised by calculating the voltage balancing capacitance of each SiC MOSFET. Experimental results demonstrate that, compared to the traditional uniform method, the NRCD balancing method reduces the maximum deviation in drain‐to‐source voltages from 80.4 V to 2.0 V and the pulse rise time from 13.0 ns to 11.4 ns at an output of 3200 V, representing a 10.8% increase in speed. At 50 kHz, the largest switching loss for devices can be reduced from 5.857 W to 3.198 W, and the efficiency of switching losses can be improved by 45.4%.