Design-for-Test (DFT) strategies for high-performance computing and graphics chips

With the architecture complexity of silicon in high-performance computing (HPC) and graphics processing units (GPUs) growing, reliability, scalability, and first-time-right silicon cannot be achieved without the introduction of advanced Design for Test (DFT) methodologies. This paper addresses the peculiarities of DFT magnetization to cope with the characteristics of HPC and GPU environment issues: massive parallelism, depth pipelining, multi-clock, power domains, and rising thermal and power density. It covers basic techniques, including scan-based testing, built-in self-test (BIST), logic BIST (LBIST), and a modular and hierarchical test planning framework. Additionally, the paper studies the related key infrastructural pieces, such as test access mechanisms (IJTAG, IEEE 1500), remote debug orchestration, and centralized test control units. Additionally, emerging trends like AI/ML-enabled ATPG, in-field telemetry, predictive maintenance, and DFT innovations in the contexts of chipset-based and 3D-integrated architecture alter the test requirements for the overall multi-die system. It provides best practices in early DFT planning, modular IP reuse, scan chain optimization, and power-aware test pattern generation to obtain high test coverage while maintaining silicon performance. This work presents actionable insights for high-yield silicon design and validation in the next-generation compute platform landscape. It is aimed at silicon architects, DFT engineers, and verification professionals.