High-performance register file design for general-purpose graphics processing unit with multi-issue logic

GPGPU requires large capacity and high performance register files to save running state and achieve seamless thread bundle switching to improve parallel performance. However, the area and power consumption of register files increase rapidly with the number of access ports, which makes it difficult for register files to adopt more radical multi-port designs. For multi-issue logic GPGPU, the limited number of ports leads to a significant increase in the probability of read and write conflicts, which severely limits the improvement of GPGPU performance. In this paper, a register file design for multi-issue logic is presented. Different from the existing single-port design, the proposed register file separates the operand read and write logic and distributes the registers interleaved to solve the register conflict from two aspects. Moreover, the improved operand collector supports parallel execution, which can fully leverage the performance of the register file. The effectiveness of the proposed method has been validated by applying GPGPU instances on an FPGA platform and designing test cases.