Design of Wallace Tree Multiplier Using Counter Architecture

As technology advances, achieving low power consumption in Integrated Circuits has become a major concern. The current priority of the designers is energy minimization for portable devices with minimal trade-offs in speed and area. Recent developments have focused on low-power multipliers for applications such as digital signal processing, which demand minimal consumption of power and tolerance for delays. The design of a counter based low power 16 x 16 Wallace tree multiplier is presented here. The reduction in the partial product stage is effectively done by employing power-efficient 7:3 counters at each stage. Low power is targeted in the proposed design. The proposed Counter-Based Wallace Tree Multiplier (CBW) is designed using Verilog language. The design is synthesized using Synopsys Design Compiler to measure the performance parameters such as power, delay, etc. Additionally, a Multiply and Accumulate (MAC) unit has been constructed utilizing the proposed multiplier to showcase its practical application. The proposed design achieves a power reduction ranging from 5.67% to 6.88% compared to the existing designs.