Analysis of Power Supply Voltage Drop and Delay in a Cascaded CMOS Inverter Circuit Using Pristine-GNR and Copper Interconnect Material

In this study, we analyzed the performance of pristine Graphene Nano Ribbon (GNR) interconnects compared to traditional Cu interconnect material. To evaluate both interconnects, we examined a ten-stage cascaded inverter chain, assessing IR drop, power consumption, delay, and power-delay product (PDP) performance. We conducted this analysis using 16nm device technology (PTM-HP model) and 16nm interconnect technology for both materials. Results show that GNR interconnects outperform Cu, with approximately 8.2times lower IR-drop, 9.3 times lower power consumption, 3 times lower delay, and 2.5 times lower PDP. All simulations were conducted in the SPICE environment, demonstrating the potential of GNR interconnects for high-speed integrated circuit design in next-generation applications.