Study of Scaling Effects and Reliability Issues in Pre-Amplifier Based Dynamic Comparator for Future High Speed Analog to Digital Converters

This study aims to investigate the consequences of power, delay and ΔVin at technology scaling as well as voltage scaling at same nano technology. The proposed comparator uses static latch at 16 nm, 22 nm, 32 nm, 45 nm and 90 nm technologies. We reveal how ΔVin performs at 16 nm for 0.2v and 0.7v results in 19.21% to 23.9% growth in delay and 14.25% - 16.17% fall in power consumption. When Clk is on we get better performance for both when Vp > Vn and Vp < Vn. The proposed comparator delay and power at 16nm are 1.16% increase and 12.25% increase successively. High precision, high speed, low power absorption are just a few benefits of comparator. When it comes to the applications of comparator it includes Schmitt triggers, zero-crossing detector, voltage-regulation, digital-to-analog converters, Op-amps and microcontrollers are some of the implementations of comparators.