Impact of Doping Profile Engineering for Enhanced Performance in Nanosheet Field Effect Transistors

In this work, we propose a detailed performance optimization study of Nanosheet Field Effect Transistors (NSFETs) using Sentaurus TCAD tool. NSFETs enabled feature scaling beyond 7-nm technology node offering improved electrostatic integrity, reduced leakage current with suppressed Short-Channel-Effects along with high current drive capability. Additionally, stacked nanosheets offer better fabrication feasibility compared to FinFETs, enabling superior performance across various sheet widths. Small signal analysis is performed to optimize device parasitics, transconductance and frequency of operation. Furthermore, to eliminate the ultra-steep doping profile in conventional NSFETs, concept of Junctionless Nanosheet FET (JL-NSFETs) has been introduced with improved device performance parameters like ON-current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>), OFF-current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>), ON-to-OFF current ratio (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>), Subthreshold Slope (SS) and Drain-Induced-Barrier-Lowering (DIBL). Moreover, to enhance current drivability, Junctionless Accumulation Mode NSFET (JAM-NSFET) is introduced with a detailed comparative analysis of performance parameters.