Designing and Utilizing of Novel Pass Transistor Logic for Low Power CMOS Full Adder

The efficiency of a system is primarily determined by the performance of its internal components. Low-power, high-speed components should be designed. A direct relationship exists between the number of transistors present in a design and its power consumption. A circuit's power consumption is heavily influenced by its transistor count. Compared with other modern low-power technologies, the idea is to introduce a logical structure that consumes low power. In this research, we propose a novel method for reducing power consumption. The result shows that the proposed technique is an efficient full adder cell with the least MOS transistor count that reduces the high-power consumption and increases the speed.