Application Mapping Approaches and Methodologies in Real-Time Network-on-Chip (NoC) Architectures

This study examines real-time Network-on-Chip (NoC) dynamic application mapping and scheduling techniques, architectures, and addresses the need for efficient task allocation in increasingly complex multicore systems. This study focused on heuristic-based, machine learning-based, congestion-aware, energy-aware, deadline-aware, hybrid, and latency-aware algorithms, evaluating their effectiveness in optimizing performance, energy efficiency, and communication latency. The methodology included a systematic analysis of recent research papers with the highest number of citations from the last dec-ade. Future work in this area needs to consider the use of AI for better compatibility, developing hybrid approaches while addressing the issues of scalability and fault tolerance in NoC-based multicore systems. This work serves as the base for further improvements in developing application mapping approaches for advanced NoC architectures.