Design And Implementation of Low Power and Low Area RISC Core Using Vedic Mathematics

This paper emphasis on development of a 16-bit RISC processor using a Vedic multiplier design which can execute more instructions, by making use of Verilog. For simulation of design, Vivado 2018.3 design suite is used. The main agenda of this work is to implement the multiplier unit under the Arithmetic and logic unit (MAC) by making use of Vedic Sutras. The core principle of Vedic mathematics revolves around simplifying traditional calculations to significantly lowering computational complexity. Apart from these components, the designed RISC Processor comprises additional blocks, such as the control unit (manages the operations) and instructions within a computer, while the data path facilitates the flow of data between various components like the register bank, program counter, and memory. The suggested RISC processor is extremely straightforward and can execute a total of 14 instructions. This work’s accomplishment lies in achieving power savings for the Multiply-Accumulate (MAC) unit and the arithmetic logic unit (ALU) when compared to traditional designs of the ALU and MAC, respectively. The delay in Multiply-Accumulate (MAC) and Arithmetic Logic Unit (ALU) decreases compared to traditional ALU and MAC, respectively. The Vedic MAC and ALU components eventually merged with more blocks within the processor, this makes resulting in the creation of a 16-bit Vedic processor. This reduces the latency and saved power in contrast to a standard processor. So, the advancement in speed of operation, scaling down the power utilization and less area consumption are the crucial features of designed processor.