Optimization of Advanced Nanoscale Dynamic Voltage Comparators for the Development Future Analog to Digital Converters

Dynamic Voltage Comparators links the analog and digital worlds in emerging applications like IOT, Artificial Intelligence (AI), Image Processing. In this work the performance& reliability of nanoscale pre amplifier based two stage DVC had been studied using SPICE tools using 16nm CMOS and a V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> ranging from 0.7 V to 1.2 V. The results reveal that DVC-I&DVC-II with a V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 0.7/1.2 V exhibited a delay of 32.11/20.35 pS and 39.61/26.32 pS at the temperature of 27<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> C and a delay of 43.65/24.2 pS and 57.17/31.27 pS at the temperature of 107<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> C. The DVC-I & DVC-II with a V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 0.7/1.2 V consumed a power of 2.67/39.43 μW and 2.639/35.09 μW at temperature 107<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> C respectively. The DVC’s offer super performance at 27<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> C with a higher V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> . But at higher V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>, DVC’s Consumes higher power also elevates in operating temperature levels to the degradation in performance of DVC’s.