Performance Impact of Source/Drain Contact Offset in ZnO TFTs: Overlap, Underlap, and Aligned

In this work, we present a double-gate (DG) ZnO thin-film transistor (TFT) featuring a top-gate (TG) and drain/source offset (L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Off</inf> ) structure under double-gate operation. The study investigates the impact of varying the offset between source/drain (S/D) and gate electrodes on the electrical performance of DG ZnO TFTs. The experimental details of the proposed DG ZnO TFTs are explained in detail. The channel conduction behavior across three proposed structural configurations: overlapping, aligned, and underlapping was analyzed using carrier concentration contour study. Performance comparisons of proposed device configurations are analyzed in terms of drain current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D7</inf>) and threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>). The overlapping configuration significantly enhances device performance, with a drain current of 2.04 mA/μm, which is 1.6 times higher than the drain current in the underlap configuration. The results of this study of this work indicate that DG ZnO TFTs with an overlapped design are suitable for high-performance applications in flexible electronics and sensing technologies.