Design and Performance Analysis of a Low Drop Out Voltage Regulator with High PSRR

The Low Dropout (LDO) voltage regulator is crucial in electronic systems, ensuring stable voltage regulation under varying load conditions. Key to designing an effective LDO is achieving a high Power Supply Rejection Ratio (PSRR) and minimizing noise. PSRR measures how well the LDO suppresses input voltage fluctuations, maintaining a stable output voltage. This work presents an LDO that accepts a 1.8V input and delivers a steady 0.8V output, with a dropout voltage of 1V. It uses a 0.4V bandgap reference for accurate voltage regulation. The LDO achieves a PSRR of -50 dB at 100 kHz, demonstrating its effectiveness in reducing supply noise. Additionally, it shows a load transient response with a maximum overshoot of 0.9V and an undershoot of 0.6V, supporting load currents up to 40 mA. The design employs an NMOS transistor as the pass element and a P-type differential input, two-stage operational transconductance amplifier (OTA) for the error amplifier. Key design parameters include a -3 dB bandwidth of 5.6 kHz, a phase margin of 60 degrees, and a loop gain of 60 dB. Developed using the 180 nm technology from the UMC library, the LDO maintains a stable 0.8V output while meeting low dropout operation criteria. Its strong PSRR performance ensures effective suppression of supply noise, making it a reliable choice for applications that require precise voltage regulation and high efficiency. This design is ideal for various electronic systems and devices where stable and efficient voltage regulation is essential.