Debug Fabrics Verification using Formal Methodology

The increasing complexity of System-on-Chip (SoC) products has amplified the potential for design bugs, necessitating robust post-silicon validation to ensure system reliability. Design-for-Debug (DFD) has become an important feature for modern and complex SoC's. DFD plays a vital role for post-silicon during silicon execution. Debug infrastructure in any SoC or Subsystem routes various forms of debug information like Triggers, raw ip signals, and packetized data through debug fabrics to SoC pins. This mandates the need for the pre-silicon to check if all the debug fabrics connections are intact within SoC. In pre-silicon this has been validated using legacy simulation-based validation mechanisms which are time consuming due to dependency on SoC models, reset flow and lengthy regressions runtime (28-48 hours) for one test scenario. Few critical bugs were found due to ignored connections and tie-offs in debug fabrics RTL which can be identified at early stage of validation using Formal Verification. This paper presents verification of the debug fabrics using formal methodology ensuring the connectivity of fabrics which was achieved in 10 mins. This helps to find the bugs prior to simulation and significantly improved the verification efficiency and it has been demonstrated through experimental results.