ASIC of Instrumentation Amplifier with High CMRR for Precision Signal Processing

This paper presents the design, simulation, and analog layout of a two-stage CMOS operational amplifier incorporating a differential amplifier with Miller compensation intended for use in a high-performance instrumentation amplifier. The primary objective is to improve the precise detection of low-level signals by achieving high gain, improved bandwidth, and improved stability. The designed CMOS instrumentation amplifier demonstrates a gain of 102.127 dB, a common-mode rejection ratio (CMRR) of 135.01 dB, and a gain bandwidth of 12.71 MHz, with a power consumption of 6.9 mW. The amplifier layout occupies an area of 67.32 μm × 42.935 μm and operates at ±1.8V using 0.18 μm technology, with simulations conducted in the Cadence Virtuoso environment. The results confirm the effectiveness of the proposed opamp design for integration into instrumentation amplifiers, enabling accurate and reliable detection of low-level signals in various applications.