An FPGA-Optimized Parallel Processor Architecture for Huff Curves with Reduced Clock Cycles

Elliptic Curve Cryptography (ECC) is extensively used for secure communications due to its strong security properties and efficiency at smaller key sizes compared to other cryptosystems. Within ECC, Binary Huff Curves (BHC) present an advantageous choice, especially in binary fields like GF(2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">233</sup>) as recommended by National Institute of Standards and Technology (NIST), due to their compact representation and unified computational framework. This unified structure enables consistent power consumption profiles during both point addition and doubling, enhancing security against side-channel attacks such as power analysis. In this paper, we propose an optimized FPGA-based architecture for accelerating point multiplication on BHC, leveraging architectural innovations to achieve significant improvements in both security and efficiency. Our approach emphasizes parallelism, employing the Non-Adjacent Form (NAF) for scalar multiplication rather than the traditional Double-and-Add method, and integrates parallelized hybrid Karatsuba multipliers along side the Hex Itoh-Tsujii algorithm for optimized field arithmetic. By focusing on a unified addition pattern, we achieve a latency of 29.5 ns on a Virtex-4 FPGA and 23.1 ns on a Virtex-7 , marking a reduction in clock cycles of up to 59.6% on Virtex-4 and 42.3% on Virtex-7 over previous designs. These optimizations establish a new benchmark for secure and efficient cryptographic processing on reconfigurable hardware.