An Area-Efficient Continuous-Time Ising Machine Featuring Dynamic Threshold Annealing

Recently, Ising machines have received rising attention as efficient alternatives for solving combinatorial optimization problems (COPs), compared to von Neumann architectures with high power consumption and prolonged latencies. While prior discrete-time Ising machines exploited near-/in-memory computing to mitigate memory access bottlenecks, their reliance on sequential spin updates inherently limits solution speed. To address this problem, continuous-time (CT) Ising machines have emerged as promising low-cost COP solvers due to their fully parallel spin-update mechanisms. However, existing CT Ising machines face a critical trilemma in simultaneously achieving multi-level coefficient precision, area-efficient spin implementations, and effective annealing strategies. In this work, we present a CT Ising machine with an eDRAM-based in-memory computing architecture. The design introduces a neighboring spin computation-sharing architecture that halves the storage overhead of interaction coefficients, thereby significantly reducing the spin cell area. Furthermore, a novel dynamic threshold annealing method is proposed to attain lower Ising Hamiltonians during the solution process. An 18 × 34 spin array has been designed in a 55-nm CMOS process, which achieves a compact spin unit footprint of merely 561 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 15-level programmable interaction coefficients. Additionally, post-layout simulation results validate that the proposed Ising machine achieves comparable nanosecond-scale time-to-solution (TTS) for diverse max-cut COPs while consuming 0.84 nJ at a 1.0 V supply voltage.