Considerations on Low-Clock-Jitter-Susceptibility DC–DC Converters and Pseudo-Average-Current-Mode-Control

In many modern applications, like AMOLED displays and RF transceivers, the need for high-quality ultralow noise regulated rails is posing serious challenges in the design of DC-DC converters capable of efficiently provide such rails. Recently, pseudo-average-current-mode-control (PACMC) has been presented as a new DC-DC converter control scheme featuring a reduced susceptibility to the clock jitter and suited for low-noise applications, but insufficient details have been disclosed. In this paper, a comprehensive study of PACMC is first provided, with a novel complete small-signal model, otherwise previously missing. Then, a fair comparison between PACMC and the widely used peak-current-mode-control (PCMC) is presented. In the thorough analyses, the most relevant performances are investigated, starting from loop stability, audiosusceptibility, sensitivity to electronic circuit noise and clock jitter, with the goal to empower the designer with a fulfilling breakdown for the selection of the most suited control scheme.