An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier

This article presents a single-channel 4-GS/s 8-bit hybrid-domain analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. The proposed 8-bit ADC combines a 3-bit voltage-domain stage with a 6-bit time-domain (TD) backend to take full advantage of the voltage and time domains. A high-speed hybrid-loop residue amplifier (RA) is proposed with a settling time of less than 150 ps, while a non-symmetrical pipeline timing utilizing a 25% duty cycle clock is used to increase the TD quantization time and the settling time margin of the RA. A low-power and small-area gated-ring-oscillator-based TD backend is employed, which operates at 4-GS/s with 6-bit resolution. The prototype hybrid ADC occupies an active area of 0.0114 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Under a 1-V power supply and Nyquist input, the chip achieves a measured ENOB of 6.46 bits at a conversion rate of 4 GS/s, while the power consumption is 10.6 mW and the FoMw is 29.9 fJ/conversion-step.