A Second-Order Continuous-Time Noise-Shaping SAR ADC With Ping-Pong DACs and <i>G</i> <sub>m</sub>-OTA-<i>C</i> Integrator
This brief presents a ping-pong continuous-time noise-shaping successive-approximation register (CT NS-SAR) analog-to-digital converter (ADC) architecture. Compared with the previous works, two ping-pong operation DACs are utilized to release the conversion time from 5% to 95% of the clock period, while ensuring the continuity of CT integration in the time domain, thus realizing the ideal noise transfer function (NTF) of the true CT-NS SAR. The DAC of each channel performs two roles of integration and conversion alternately, not only converting the signal in the current period but also bringing the generated residue voltage into the next period. Besides, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-OTA-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator replaces the open-loop <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator, where the OTA isolates the output parasitic capacitance, achieving an exact CT integration. The effective conversion bits are calculated by the bandwidth (BW) and the time of bit cycle, thus avoiding the redundant bits. Verified by postsimulation in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB over 20-MHz BW with an oversampling ratio (OSR) of 15. Under a 1.2-V supply voltage, the ADC consumes 2.3 mW and exhibits a Schreier figure of merit (FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{ {S}}$</tex-math> </inline-formula>) of 170.2 dB.
Authors
- Yanbo Zhang
- Zhangming Zhu (ORCID: https://orcid.org/0000-0002-7764-1928)
- Xin-Xin Zhong
- Guolong Fu
Institutions
- Xidian University (CN)
Publication Details
- Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2025-05-08
- DOI
- https://doi.org/10.1109/tvlsi.2025.3563474
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- National Key Research and Development Program of China
- Fundamental Research Funds for the Central Universities