Comparative Analysis of Interleaving Schemes in High-Speed Digital-to-Analog Converters
The growing interest in interleaved digital-to-analog converters (DACs) has led to numerous developments and designs, while extending interleaving factors poses several challenges. This research presents a hybrid segment architecture for expanding the number of channels in time-interleaved (TI)-DACs, addressing critical limitations of existing architectures. Our architecture incorporates a pre-filter, a single-stage analog multiplexer, and an output combiner, enabling improved performance and compromising bandwidth and usable output swing. In addition, a comprehensive system-level analysis is conducted in this paper to evaluate the performance of different TI-DAC architectures. The simulation result highlights the effectiveness of the hybrid architecture in achieving superior SNR with sufficient bandwidth and overcoming the challenges of channel number extension.
Authors
- Akio Higo (ORCID: https://orcid.org/0000-0002-4595-0929)
- Tetsuya Iizuka (ORCID: https://orcid.org/0000-0002-1512-4714)
- Zolboo Byambadorj (ORCID: https://orcid.org/0000-0003-3859-4169)
- Yunjie CHEN
- Koji Asami (ORCID: https://orcid.org/0000-0002-8263-4423)
Institutions
- Tokyo University of Information Sciences (JP)
- The University of Tokyo (JP)
Publication Details
- Journal
- IEICE Transactions on Electronics
- Published
- 2025-05-08
- DOI
- https://doi.org/10.1587/transele.2024ctp0002
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- University of Tokyo
- Japan Society for the Promotion of Science