Comparative Analysis of Interleaving Schemes in High-Speed Digital-to-Analog Converters

The growing interest in interleaved digital-to-analog converters (DACs) has led to numerous developments and designs, while extending interleaving factors poses several challenges. This research presents a hybrid segment architecture for expanding the number of channels in time-interleaved (TI)-DACs, addressing critical limitations of existing architectures. Our architecture incorporates a pre-filter, a single-stage analog multiplexer, and an output combiner, enabling improved performance and compromising bandwidth and usable output swing. In addition, a comprehensive system-level analysis is conducted in this paper to evaluate the performance of different TI-DAC architectures. The simulation result highlights the effectiveness of the hybrid architecture in achieving superior SNR with sufficient bandwidth and overcoming the challenges of channel number extension.

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Publication Details

Journal
IEICE Transactions on Electronics
Published
2025-05-08
DOI
https://doi.org/10.1587/transele.2024ctp0002
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.00

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article

Comparative Analysis of Interleaving Schemes in High-Speed Digital-to-Analog Converters

Akio Higo, Tetsuya Iizuka, Zolboo Byambadorj, Yunjie CHEN et al.
IEICE Transactions on Electronics
Analog and Mixed-Signal Circuit Design
article

Comparative Analysis of Interleaving Schemes in High-Speed Digital-to-Analog Converters

Akio Higo, Tetsuya Iizuka, Zolboo Byambadorj, Yunjie CHEN, Koji Asami
article en

Abstract

The growing interest in interleaved digital-to-analog converters (DACs) has led to numerous developments and designs, while extending interleaving factors poses several challenges. This research presents a hybrid segment architecture for expanding the number of channels in time-interleaved (TI)-DACs, addressing critical limitations of existing architectures. Our architecture incorporates a pre-filter, a single-stage analog multiplexer, and an output combiner, enabling improved performance and compromising bandwidth and usable output swing. In addition, a comprehensive system-level analysis is conducted in this paper to evaluate the performance of different TI-DAC architectures. The simulation result highlights the effectiveness of the hybrid architecture in achieving superior SNR with sufficient bandwidth and overcoming the challenges of channel number extension.

IEICE Transactions on ElectronicsVol. E108.C(10)
Tokyo University of Information Sciences (JP), The University of Tokyo (JP)
University of Tokyo, Japan Society for the Promotion of Science
Affordable and clean energy
Openalex Percentile: Top 91%
Analog and Mixed-Signal Circuit Design
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Comparative Analysis of Interleaving Schemes in High-Speed Digital-to-Analog Converters — Akio Higo, Tetsuya Iizuka, et al. · IEICE Transactions on Electronics (2025) | TGRS Research Map | TGRS