First demonstration of leaky-integrate and fire neuron based GAA nanosheet FET with ultra-low energy consumption down to 0.8fJ/spike for spiking neural network applications

Abstract The fundamental component of an artificial spiking neural network (SNN) is an electronic device designed to emulate a biological neuron effectively. However, a key concern is the high energy consumption and large area associated with these artificial neurons, rendering them highly inefficient. This article presents a CMOS-compatible Gate-All-Around Nanosheet Field-Effect Transistor (GAA NSFET)-based Leaky Integrate-and-Fire (LIF) neuron with gate length of 50 nm. This design achieves an exceptionally low energy consumption of 0.8 fJ, thereby establishing a new benchmark in the field. Utilizing well-calibrated 3D TCAD simulation and the SRH recombination model, along with the Unibo2 model to represent impact ionization phenomena, the proposed GAA NSFET LIF neuron effectively captures integration and recombination aspects within it. Moreover, it operates with a supply voltage of merely 1.8 V, significantly lower than conventional bulk FinFET and PD-SOI MOSFET-based LIF neurons. Also, it demonstrates spiking frequency of ~100 MHz, approximately <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msup> <mml:mrow> <mml:mn>10</mml:mn> </mml:mrow> <mml:mrow> <mml:mn>5</mml:mn> </mml:mrow> </mml:msup> </mml:math> times higher than that of a biological neuron, controlled by the input voltage of the device, allowing the neuron adapt dynamically. Nanosheet FET technology offers superior electrostatic control, minimizing parasitic capacitances and facilitating rapid switching capabilities, thereby optimizing both power and performance simultaneously. Furthermore, the effective area of the NSFET amounts to <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msup> <mml:mrow> <mml:mn>0.004</mml:mn> <mml:mspace width="0.5em"/> <mml:mi mathvariant="normal">μ</mml:mi> <mml:mi mathvariant="normal">m</mml:mi> </mml:mrow> <mml:mrow> <mml:mn>2</mml:mn> </mml:mrow> </mml:msup> </mml:math> , making it an appealing choice for low-power, area-efficient, large-scale hardware implementations of SNN applications.