Suppressing the Surface Roughness of InZnGeO Film and Enhancing TFT Performance by Stacking InZnGaO Layer

In this study, the effects of capping an InZnGaO layer on the In-rich InZnGeO film and associated thin film transistors (TFTs) were demonstrated. By introducing an InZnGaO layer and a subsequent annealing process, the channel surface roughness becomes smoother with a root mean square (rms) roughness from 2.250 to 0.672 nm. And the InZnGaO capped InZnGeO TFT shows a field effect mobility significantly increased by 37.5%. This improvement is due to the InZnGaO/InZnGeO structure not only protects the surface of the In-rich film, but also forms a heterojunction providing an additional path for carrier transport. Finally, we obtained that TFT with a field effect mobility of 22.35 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup>⋅<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</roman><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-<roman>1</roman></sup>⋅<roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</roman><sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-<roman>1</roman></sup>, exhibiting a low subthreshold swing (SS) of 0.24 V/dec, a threshold voltage of -0.16 V, and a threshold voltage drift of only -0.97 V after applying a positive gate bias stress of 20 V for 3600 s in a working environment of 70 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C. Therefore, indicating that an InZnGaO layer stacking on an In-rich film can reduce surface roughness and trap states to protect the In-rich channel and enhance the TFT performance.