Switching Controllability for SiC JFET/Si IGBT Cascode With External Absorption and Boost Capacitors

Silicon-based insulated gate bipolar transistor (Si IGBT) is a crucial device in high-power systems. However, the enormous switching loss (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub>) has always been the primary problem that limits its applications. To reduce <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub>, inspired by the SiC JFET/Si MOSFET Cascode (SSMC), a SiC JFET and low voltage Si IGBT Cascode (L.SSIC) is proposed and validated by experiment and technology computer aided design (TCAD) simulation . In the ON-state, due to the bipolar conduction mode, the L.SSIC has stronger current conductivity than SSMC. But the tail current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tail</sub>) is still serious during turn-off transient. To optimize the switching transient and eliminate <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tail</sub>, an absorption capacitor (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub>) and a boost capacitor (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub>) are adopted in L.SSIC. Through switch characteristic testing, the proposed L.SSIC with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> is verified. The research results show that the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> of L.SSIC is 42.5% lower than that of conventional Si IGBT at 600 V/60 A. At the current of 80 A and switching frequency of 200 kHz, the power loss of L.SSIC is 26.8% and 6.9% lower than that of the SiC MOSFET and SSMC, respectively. Additionally, In boost circuit testing, under a duty cycle of 70% and working current of 20 A, the L.SSIC achieves similar conversion efficiency to SiC MOSFET. The advantage become more apparent as the operating current increases.