Design Techniques for a Multi-Phase Injection- Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers

Clock generation for high-speed wireline receivers must provide multiple clock phases with high-resolution rotation. To address this, an 8-phase 17 GHz clock generation circuit with built-in 6b rotation is presented. Multi-phase injection is used to perform reference-side phase rotation to efficiently generate and rotate eight clock phases. The injection method is analyzed with a model to study the introduced nonlinearity, and the effect of the injection strength is discussed. Designed by using BAG3++ for layout-aware design optimization, the proposed circuit achieves 98 fs RMS jitter and a measured DNLpp and INLpp of 1.26 and 4.05 LSB respectively, while consuming 33 mW.

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Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2025-05-07
DOI
https://doi.org/10.1109/tcsi.2025.3563517
Citations
1
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.73
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article

Design Techniques for a Multi-Phase Injection- Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers

Borivoje Nikolić, Bob Zhou
1 citations
IEEE Transactions on Circuits and Systems I Regular Papers
Radio Frequency Integrated Circuit Design
0.73
article

Design Techniques for a Multi-Phase Injection- Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers

Borivoje Nikolić, Bob Zhou
article en
1 citations

Abstract

Clock generation for high-speed wireline receivers must provide multiple clock phases with high-resolution rotation. To address this, an 8-phase 17 GHz clock generation circuit with built-in 6b rotation is presented. Multi-phase injection is used to perform reference-side phase rotation to efficiently generate and rotate eight clock phases. The injection method is analyzed with a model to study the introduced nonlinearity, and the effect of the injection strength is discussed. Designed by using BAG3++ for layout-aware design optimization, the proposed circuit achieves 98 fs RMS jitter and a measured DNLpp and INLpp of 1.26 and 4.05 LSB respectively, while consuming 33 mW.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 72(9)
University of California, Berkeley (US)
Affordable and clean energy
Openalex Percentile: Top 29%
Radio Frequency Integrated Circuit Design
0.73
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Design Techniques for a Multi-Phase Injection- Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers — Borivoje Nikolić, Bob Zhou · IEEE Transactions on Circuits and Systems I Regular Papers (2025) | TGRS Research Map | TGRS