Design and Implementation of a Power-Efficient 32-bit MAC Unit Using Vedic Multiplier and 64-bit CLA with Clock Gating for FPGA-Based Applications

This study presents development and implementation of a power-efficient architecture of a 32-bit MAC Unit built with Verilog HDL for FPGA applications. This architecture also connects a Vedic multiplier to boost multiplication, along with a architecture of 64-bit CLA and 64-bit MAC Unit accumulator to facilitate rapid accumulation with reduced propagation delay. To reduce power, RTL clock gating is used to eliminate unnecessary switching activities. To check correctness and performance of the proposed ISUM design, we perform simulation and verification in Xilinx Vivado. Post-synthesis verification results on important parameters such as timing, resource usage and dynamic power are presented and reveal significant improvements over traditional MAC architectures. Furthermore, the design is scalable, allowing higher bit width computations to be performed with very few modifications. The architecture is a computing element with better performance in terms of performance and energy codes, a comparative study with the correct MAC units will show that the MAC processing elements are the most suitable units for high-performance DSP and AI-driven FPGAs