Simulation on the Miniaturization and Performance Improvement Study of Gr/MoS₂ Based Vertical Field Effect Transistor

Abstract Vertical field effect transistors (VFETs) show many advantages such as high switching speed, low operating voltage, low power consumption, and miniaturization over lateral FETs. Graphene (Gr) and transition metal di‐chalcogenides (TMDs) are attractive 2D materials for the next generation electronics due to their subnanometer monolayer thickness. The layer by layer structure in 2D materials allows device fabrication down to a monolayer or a few layers, hence advantageous for VOFETs. In this simulation work, the bulk molybdenum disulfide (MoS 2 ) is sandwiched between perforated monolayer graphene which acts as the source electrode, and aluminum (Al) as the top drain electrode. In addition to this, the minimization of the off‐state current is carried out by modifications in the source contact geometry by insulating some part of the source electrode and introducing the extra MoS 2 layer between the source and gate dielectric named as buried layer. After the modification, the results show an improvement in OFF current, hence the ON/OFF ratio. The ON/OFF ratio of 10 6 is achieved for the device with a gate width and channel length of 100 nm. Additionally, the gate width is miniaturized to 50 nm by introducing insulation on the source contact to achieve similar performance.