THE HDL IMPLEMENTATION OF HIGH SPEED FIR FILTER USING SA-COMPRESSORS AND OPTIMIZED APPROXIMATE ADDERS USING FPGA

Finite Impulse Response (FIR) filters are widely used in digital signal processing (DSP) applications due to their stability and linear-phase characteristics.However, their high computational complexity, primarily due to extensive multiplication and addition operations, can limit their speed and efficiency.In this paper we present a high-speed FIR filter design by integrating segmented arithmetic (SA) based compressors and approximate adders to enhance computation speed.The proposed approach replaces conventional adder trees with segmented arithmetic (SA) based compressor circuits (such as 4:2 and 7:3 compressors), which efficiently reduce partial