A Novel Reconfigurable Gate-Biasing Technique for Extending Dynamic Range in CMOS RF-DC Rectifiers Targeting RFEH Applications

This paper presents a novel fully integrated radio frequency (RF) rectifier tailored for a wide power dynamic range (PDR) with multiband adaptability to efficiently convert AC RF power into DC power. The proposed rectifier utilizes the strength of interstage gate biasing to achieve high power conversion efficiency (PCE) across a broad range of input power levels. Through its reconfigurable mode, the circuit seamlessly transitions between a low-power path and high-power path to ensure optimal performance across a wide PDR. Simulated using CMOS 65 nm technology, the post-layout assessment reveals a peak PCE of 48.8% at 900 MHz and 46.4% at 1800 MHz, with an extensive PDR of 20 dB for PCE exceeding 20% at both frequencies.

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Publication Details

Journal
Chips
Published
2025-05-06
DOI
https://doi.org/10.3390/chips4020022
Citations
2
Primary Topic
Energy Harvesting in Wireless Networks
Type
article
Field-Weighted Citation Impact
1.46
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article

A Novel Reconfigurable Gate-Biasing Technique for Extending Dynamic Range in CMOS RF-DC Rectifiers Targeting RFEH Applications

Wen Xun Lian, Harikrishnan Ramiah, Yi Chen Lee, Y.L. Low
2 citations
Chips
Energy Harvesting in Wireless Networks
1.46
article

A Novel Reconfigurable Gate-Biasing Technique for Extending Dynamic Range in CMOS RF-DC Rectifiers Targeting RFEH Applications

Wen Xun Lian, Harikrishnan Ramiah, Yi Chen Lee, Y.L. Low
article en
2 citations

Abstract

This paper presents a novel fully integrated radio frequency (RF) rectifier tailored for a wide power dynamic range (PDR) with multiband adaptability to efficiently convert AC RF power into DC power. The proposed rectifier utilizes the strength of interstage gate biasing to achieve high power conversion efficiency (PCE) across a broad range of input power levels. Through its reconfigurable mode, the circuit seamlessly transitions between a low-power path and high-power path to ensure optimal performance across a wide PDR. Simulated using CMOS 65 nm technology, the post-layout assessment reveals a peak PCE of 48.8% at 900 MHz and 46.4% at 1800 MHz, with an extensive PDR of 20 dB for PCE exceeding 20% at both frequencies.

ChipsVol. 4(2)
Asia Pacific University of Technology & Innovation (MY), University of Malaya (MY)
Openalex Percentile: Top 18%
Energy Harvesting in Wireless Networks
1.46
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