Securing RISC-V SoC With Random Clock Self Complementary Countermeasure

The growth of IoT across industries, has made secure communication crucial, especially in resource-limited, power-constrained SoCs. The major contributions of this work are the design of an area and power efficient cryptographic RISC-V SoC by integrating AES hardware accelerator IP with RISC-V, and the development of a secure cryptographic RISC-V SoC using the Random Clock Self Complementary (RCSC) countermeasure against PAA. RCSC enhances security by introducing amplitude and timing variability through complementary operations on random numbers and utilizing variable number of clock cycles per encryption. The design is tested and power traces for PAA were generated on both ASIC and FPGA platforms. The design achieves minimal power overhead of 0.407%and hardware costs of 7.33%, with strong resilience to PAA. It is evidenced by an MTD greater than one million, SNR below 0.5, MI in milli-range, and TVLA within +/-4.5, allowing the SoC to withstand attacks with over one million power traces.