3D-DRAM Si/SiGe superlattices: inspection strategies and evaluation

The growing interest in using Si/SiGe as a foundational material for 3D stackable DRAM and logic devices presents a significant challenge for inspection strategies, given the defect length scales, density and relative positions.1,2 Ensuring the quality of these templates is crucial to minimize current leakage and achieve high electrical efficiency. In this study, we explored various types of Si/SiGe-specific crystalline defects (e.g., misfits, threading dislocations and crosshatch), their z-positions (through stack, surface, at interface) and established correlations using multiple measurement techniques across a wide range of defect-specific interactions with various spectroscopic and microscopic techniques. High-throughput techniques like optical inspection and x-ray topography (XRT) were examined in their effectiveness in identifying misfits based on various physical characteristics. Additionally, high-resolution review techniques such as ebeam and atomic force microscopy (AFM) were tested to assess their ability to detect individual surface misfits and validate inspection results. The balance between throughput, sensitivity, and defect density was also analysed to optimize the detection capabilities of these techniques. Detecting threading dislocations (TDs) as a key objective was investigated using Electron Channelling Contrast Imaging (ECCI). While ECCI is a benchmark reference technique for TD detection, it faces significant throughput challenges. Despite these limitations, the presence of threading dislocations at the ends of misfits on 300mm wafers was identified. In summary, examining Si/SiGe-specific crystalline defects with a blend of high-throughput and high-resolution techniques is essential for optimizing the quality of Si/SiGe superlattices on 3D-DRAM and logic devices. This comprehensive approach can facilitate the development of more efficient inspection strategies, resulting in improved device reliability and electrical efficiency.

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Published
2025-05-06
DOI
https://doi.org/10.1117/12.3052524
Citations
2
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
1.46
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article

3D-DRAM Si/SiGe superlattices: inspection strategies and evaluation

Gerhard Bast, Masoud Dialameh, Roger Loo, Markus Kühn et al.
2 citations
Integrated Circuits and Semiconductor Failure Analysis
1.46
article

3D-DRAM Si/SiGe superlattices: inspection strategies and evaluation

Gerhard Bast, Masoud Dialameh, Roger Loo, Markus Kühn, Miki Isawa, Johan Meersschaut, Kaoru Fukaya, Christian Kranert, Dorin Cerbu, Anne-Laure Charley, Alain Moussa, Attilio Belmonte, Nachiketa Janardan, Christophe Béral, A. Vigliante, K. Chirko, Gaetano Santoro, Gian F. Lorusso, Andrew Cross, Gouri Sankar Kar, Matteo Beggiato, C. Reimann, Han Han, Wei Sun, Andrew Cockburn, Janusz Bogdanowicz, Paul Wimmer
article en
2 citations

Abstract

The growing interest in using Si/SiGe as a foundational material for 3D stackable DRAM and logic devices presents a significant challenge for inspection strategies, given the defect length scales, density and relative positions.1,2 Ensuring the quality of these templates is crucial to minimize current leakage and achieve high electrical efficiency. In this study, we explored various types of Si/SiGe-specific crystalline defects (e.g., misfits, threading dislocations and crosshatch), their z-positions (through stack, surface, at interface) and established correlations using multiple measurement techniques across a wide range of defect-specific interactions with various spectroscopic and microscopic techniques. High-throughput techniques like optical inspection and x-ray topography (XRT) were examined in their effectiveness in identifying misfits based on various physical characteristics. Additionally, high-resolution review techniques such as ebeam and atomic force microscopy (AFM) were tested to assess their ability to detect individual surface misfits and validate inspection results. The balance between throughput, sensitivity, and defect density was also analysed to optimize the detection capabilities of these techniques. Detecting threading dislocations (TDs) as a key objective was investigated using Electron Channelling Contrast Imaging (ECCI). While ECCI is a benchmark reference technique for TD detection, it faces significant throughput challenges. Despite these limitations, the presence of threading dislocations at the ends of misfits on 300mm wafers was identified. In summary, examining Si/SiGe-specific crystalline defects with a blend of high-throughput and high-resolution techniques is essential for optimizing the quality of Si/SiGe superlattices on 3D-DRAM and logic devices. This comprehensive approach can facilitate the development of more efficient inspection strategies, resulting in improved device reliability and electrical efficiency.

Seigakuin University (JP), Ghent University (BE), Applied Materials (Israel) (IL), Material (Belgium) (BE), IMEC (BE), Fraunhofer Institute for Integrated Systems and Device Technology (DE), Hitachi High-Tech (Japan) (JP), Hitachi (Japan) (JP)
Openalex Percentile: Top 18%
Integrated Circuits and Semiconductor Failure Analysis
1.46
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